In 2001, National Institute of Standards and Technology (NIST) approved Rijndael asrnAdvanced Encryption Standard(AES).Since its approval, AES is being used widely in differentrnsecurity applications for its good security, simple design and hardware suitability.AES can bernused to encrypt any digital information including videos, images and texts.Since the algorithmrninvolves several iterations, there is still a challenge for high performance implementation.Therernare some cryptographic applications which demand a higher data throughput implementationrnof the algorithm.Many researches were done on improving its performance for specific application.rnIn this thesis ,we presented a higher data throughput implementation of AES 128 bitrnencryption module for FPGA technology than the previous works in the litrature.We startedrnby exploring different available architectures for high throughput design.Then ,FPGA specificrnfeatures were studied and incorporated in the implementation to improve the throughput of thernalgorithm.A fully unrolled and pipelined architecture together with pre calculated and storedrnkey values for each rounds is used.We have used VHDL as a hardware description language.Thernsoftware used for this work is Xilinx ISE design suite 12.3.This tool is used for writing, debuggingrnand also for Synthesis Place and Route. Simulation and checking the performance resultsrnwere done using the simulation tool ISim Simulator available with the software.From the synthesisrnresult we obtained ,the system runs at 450.532MHz and has a throughput of 57.668 Gbps.