Leakage Aware Hardware Architecture And Dynamic Power Scheduling

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In the last couple of decades, battery powered mobile devices such as smart phones have becomernone of the most prolific electronic devices in history. With this has come an exploding demandrnfor performance and features that cover almost every aspect of our digital multimediarninterconnected lives including 3-D gaming, still and video cameras, WAN, Bluetooth, highspeedrndata connections, and so on. As ever increasing features continue to be integrated intornthese products, there is an ongoing need to develop innovative ways to reduce powerrnconsumption and extend battery life.rnA core requirement of effective and efficient management of energy is a good understanding ofrnwhere and how the energy is used: how much of the system’s energy is consumed by which partsrnof the system and under what circumstances.rnIn this work, a Smartphone is developed, hereafter referred to as the XLP, from the ground uprnwith modular architecture where each module is supplied through an active switch matrix whichrnis memory mapped and updated periodically by the main applications processor in the system.rnThe basic notion of this architecture is achieving zero-leakage power for modules which are notrnbeing used. This significantly reduces the idle power consumption which accounts for more thanrn60% of the average power consumed in smart phones. In addition to this novel approach on thernhardware architecture, a stochastic dynamic power scheduling and on-demand power and clockrngating policies are developed. A number of possible policies are presented and, under givenrnconditions, one of them is proved to be optimal using the energy response time product (ERP)rnmetrics.rnThe XLP is compared with three commercial smart phones, Openmoko Freerunner, HTC Dreamrnand Google’s Nexus One on similar tests and usage scenarios. The XLP and all these threerndevices use the ARM microprocessor and run the Linux kernel. The comparison is onrnperformance and power consumption. The XLP is proved to have the lowest power consumptionrnon competitive performance levels.

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Leakage Aware Hardware Architecture And Dynamic Power Scheduling

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