Ascertaining correct operation of digital logic circuits requires verification of functional behaviorrnas well as correct operation at desired clock speed. The maximum allowable clock rate in arndigital circuit is determined by the propagation delays of the combinational logic networkrnbetween latches. If the delay of the manufactured network exceeds specifications due to somernphysical defects or process variations, non-confidential and possibly incorrect logic values mayrnbe latched in memory elements. In this thesis, we present novel and efficient model for pathrndelay faults specifically for stack at fault in combinational logic circuits.rnWe propose new and efficient Model for delay fault analysis, test generation and fault simulationrnof path delay faults in combinational logic circuits. Then the new model was analyzed usingrnreduced order binary decision diagram of the Colorado University Decision Diagram package.rnAn approach for selecting critical paths along which testable path delay faults can exist isrnpresented. The proposed method is particularly helpful on path intensive circuits (large numberrnof paths). Critical paths are selected implicitly with the aid of a combination of decisionrndiagrams.rnIdeally, all the path delay faults of a circuit should be tested. However, a circuit may have a veryrnlarge number of paths, making it impossible to target all the path delay faults explicitly duringrntest generation or fault simulation. The large numbers of paths in practical circuits lead to the usernof path selection, where only subsets of the path delay faults in circuits are targeted for testrngeneration, in this case only high-risk paths. To reduce our efforts for finding test vectors, whichrnin turn reduce testing memory and processor power and analyzing a circuit for its faults, we tryrnto use reduced faults. Reduced faults can be obtained by eliminating redundant ones and ignoringrnsome that do not occur often or by eliminating faults that have the same output effect by faultrncollapsing rules.The effectiveness of the approach is demonstrated on path intensive internationalrnsymposium on circuits and systems (ISCAS'85) and International Transmission Companyrn(ITC'99) benchmarks.rnKeywords:-High-risk Paths, Delay Fault Model, ROBDD, Fault reduction