The goal of this thesis is to develop carbon nanotube field effect transistorsrn(CNFETs) based static random-access memory (SRAM) and implement it into a Very-highspeedrnintegrated circuit Hardware Description Language Analog and Mixed-Signal (VHDLAMS).rnTo achieve this objective, a compact model of the transistor known as enhancementmodernMOSFET-like SWCNT-CNFET is used. This circuit-compatible model of CNFET isrndescribed using VHDL-AMS and tested for basic electrical characteristics. This model isrnvalid for CNFETs with channel lengths greater than 20 nm. Based on the CNFETs a newrnSRAM is designed, and implemented in VHDL-AMS. The performance of the proposedrnSRAM cell is investigated and compared with SRAMs from conventional metal-oxidernsemiconductor field effect transistors (MOSFETs). The effect of substrate biasing a CNFETrnis also demonstrated and implemented in designing the SRAM cell. The VHDL-AMS codesrnof the CNFET and the SRAM are simulated in software known as Ansoft Simplorer.rnThe compact model of the CNFET is organized hierarchically in three main levels.rnThe first level models the intrinsic channel just beneath the gate of the transistor. Thernsecond level builds upon the first level and models the doped source and drain regions ofrnthe CNFET. The last level represents the complete trans-capacitance model of the transistorrnand accounts for multiple CNTs.rnThe proposed SRAM cell is composed of four CNFETs and two load resistors. Therndriver CNFETs of the proposed SRAM cell are substrate biased. Besides, 8-bit completernSRAM architecture based on this cell is indicated. The performance analysis of the SRAMrnshows that it has better writing and reading speed as well as better stability when comparedrnwith SRAM from conventional MOSFETs. Specifically, the newly proposed SRAM cellrnhas read time of twenty five pico seconds, write time of twenty pico seconds and canrntolerate a noise of 120 mV at 32 nm node technology.